Design Tools: Characterizing 10+ Gb/s Channels
By Bob Hult, Bishop & Associates Inc. 

In the past, the design of high-speed circuits was a relatively simple process of trial and error, tempered by experience. Circuit performance was typically advanced in incremental steps, which levered off prior success and minimized risk. A new circuit was commonly “breadboarded,” which consisted of building a prototype printed circuit board (PCB) in an internal shop or at an external quick-turn prototype contractor. A first-article sample system could be tested to meet the design expectations. If the system failed—which was common on the first iteration—adjustments to the design would be made, and another prototype built and tested. The cycle continued until a satisfactory design was achieved. This process seemed adequate for systems that operated at sub-gigabit clock speeds and where design cycle times permitted this multi-step process. The evolution of channels, which required differential-pair signaling with tightly-controlled impedance and skew, made the successful circuit design process more challenging. As PCB layer counts increased from four layers to more than 20 layers, breadboarding became impractical.

As channel speeds increase, it becomes more difficult to deliver a recognizable signal at the far end of a channel. A host of factors—including attenuation, crosstalk, skew, jitter, reflections, switching noise, and return loss—nibble away at the quality of the signal. Intersymbol interference (ISI), a form of noise created by high-speed bitstreams, increases significantly as data transfer rates approach 10 Gb/s. A new engineering specialty of signal integrity (SI) was born to address these issues.

Critical net circuits are designed and computer-modeled using several variations of a software called Simulation Program with Integrated Circuit Emphasis (SPICE). Its a high-speed circuit simulator that allows engineers to build a mathematical model of each element in a proposed circuit, and then simulate its performance. The results allow an analysis of how a channel will perform, including how it may be influenced by adjacent circuits. Problems can be identified, corrected, and retested to verify performance. The use of simulation tools, such as SPICE, eliminates the need to physically build prototypes until problems are worked out, reducing the design cycle. The likelihood that a new design will work the first time is greatly increased.

As the imperative of circuit simulation became widespread, connector manufacturers began to offer single and multi-line models of their connectors, which allowed designers to plug them in with active device models to increase the reliability of channel simulations. Accuracy of these models has improved because they are compared with physical measurements and verified at up to 10 Gb/s.

Designers also take advantage of evaluation test boards provided by connector manufacturers to verify circuit design. These boards are fabricated using a variety of trace designs, channel lengths, board stack-ups, PCB materials, and high-speed connectors. Engineers are able to inject signals specific to their design into the test boards. This process helps determine the best combination of factors to approximate the anticipated circuit environment. The use of development boards has minimized the need to build costly custom prototype development boards.

Data generated by Time Domain Reflectometry (TDR) equipment is another valuable tool used to evaluate channel performance. Maintaining controlled impedance throughout a link is critical to minimize attenuation and distortion. TDR measurements provide a visual representation of signal integrity and can be used to identify the source of impedance discontinuities. Working very much like radar, a fast pulse is introduced at one end of a channel and reflections are plotted against time.

Variations in impedance along the signal path will cause reflections that are displayed as a visual representation of signal propagation through the circuit.

The location of a specific discontinuity in the link can be resolved to millimeters.

Bit Error Rate (BER) is another measure of a system’s ability to convey high-speed streams of data. BER is defined as the ratio of the number of bits received incorrectly (errors) divided by the total number of bits received. Errors include those in the bitstream itself, as well as those created by the transmission system. Electronic systems today may specify bit error rates of 10‾¹² (one error in a million, million bits). Running a test routine that could generate this number of bits could take weeks. An eye diagram—a quicker, albeit imperfect, tool—can provide some insight into the probable BER of a circuit.

Higher speed digital systems stimulated the need for a quick way to check the quality of a received signal. Eye diagrams have become a valuable tool in channel analysis as they can be used to visualize how effectively the channel delivers recognizable data.  

A pattern of differential signals is injected into a test circuit and is repeatedly sampled on an oscilloscope. The resulting overlaid voltage/time measurements create a visual representation of the health of the channel.

The opening in the center is called the “eye.” A large opening indicates a low BER and high probability of delivering a clear data signal.

A number of factors tend to degrade the signal, including the length of the channel. A high-speed signal transmitted over one meter of cable produces a well-defined eye.

The same signal over 10 meters of cable shows the degradation of the signal. A “closed eye” sends the engineer back for redesign of the circuit.

The advent of multi-gigabit serial data transfer rates, together with competitive pressure to hit new target market windows, has driven system designers to find a faster more efficient process to verify new design performance. The imperative is to design systems that work the first time. Some industry standards now define the dimensions of a “mask” in the center of the eye. If a circuit’s eye pattern does not impinge the area of the mask, it will likely meet the minimum performance requirements of the standard.

The eye-diagram concept has been expanded to analyze channels with BER as low as 10ˉ¹², as conventional eye diagrams become less useful in circuits with these lower error rates. Statistical Eye (StatEye) analysis allows the engineer to reasonably predict eye diagram and BER performance using a relatively small number of bits. The resulting plot shows the eye width and height at different BER levels.

Eye diagrams are excellent tools to get a quick snapshot of channel quality, but they provide only limited data to indicate the source of problems or any solutions.

Measurements in the time domain are considered an efficient circuit analysis tool, but frequency domain circuit characterization using Scattering Parameters (S-parameters) can provide insight into the specific sources of signal loss, distortion, and electromagnetic interference that contribute to higher BERs.

S-parameters are a series of measurements that describe how high-speed signals interact with each element in a channel in terms of amplitude and phase. The resulting data can provide highly detailed information on the performance of the channel. SPICE simulations using S-parameter inputs result in more accurate predictions of multi-gigabit circuit performance. S-parameters are also used to create StatEye charts, which determine the likelihood of errors resulting from the characteristics of the channel. S-parameters have become a prime analysis tool and connector manufacturers have begun documenting their high-speed interfaces using S-parameter data. The low cost and familiarity of TDR-generated data has resulted in the introduction of conversion software that can derive S-parameter data from TDR measurements. For instance, IConnect software from Tektronix enables engineers to analyze sources of interconnect jitter, losses, crosstalk, reflections, and ringing, in both the time and frequency domains.

Channels designed for more than 10 Gb/s performance are the current target for circuit designers, but there is little practical experience available in developing successful designs at this data rate. IEEE 802.3ap is at the leading edge of standardizing 10 Gb/s differential pairs on 1-meter backplanes with a BER of 10ˉ¹² or better. This specification is the first to include a methodology for verifying performance at these frequencies. The specification defines limits on insertion loss, ripple, and insertion-loss-to-crosstalk-ratio (ICR). The signal integrity community has largely adopted this model for quantifying 10 Gb/s, or more, channels.

Connector manufacturers continue to expand the circuit development and analysis tools to their customers in the form of verified footprint models, recommended board stack-ups, and expanded libraries of connector models based on S-parameters. Some of these resources are now available online to provide around-the-clock support.

Bishop & Associates Comments

• Higher channel speeds demand a rigorous process of design, model, simulation, and verification with measurement.

• Test equipment capable of analyzing channels more than 10 Gb can easily exceed $100,000, which puts pressure on smaller design shops with limited resources, and make availability of design support from component sources more important.

• Systems designed to operate at 1 Gb/s and above are most effectively evaluated using S-parameter inputs.

• Connector manufacturers are providing an increasing array of design support tools to facilitate the successful implementation of their high-speed products.

• Eye diagrams and StatEye are useful tools, but provide only limited insight on the performance of a high-speed channel. Newer benchmarks now being introduced, such as the IEEE 802.3ap standard, may offer a more comprehensive blueprint for 10+ Gb channel characterization.

• As success in designing 10+ Gb/s circuits is developed, confidence will grow the ability to address the next leaps in technology to 40 Gb/s, and perhaps 100 Gb/s, systems.

Robert Hult
Director of Product Technology, Bishop & Associates, Inc.
Robert Hult has been in the connector industry for more than 36 years. Hult began his career as a sales engineer for Amphenol. He joined AMP in 1972 and served in several management positions through 1996. In 1997, Hult joined Foxconn as group marketing manager for Intel in Chandler, Arizona, USA. Prior to joining Bishop & Associates, Hult was the regional application engineering manager for Tyco Electronics.

Hult graduated in 1968 from Bradley University with a Bachelor of Science degree in electronics technology and a minor in business.