ESD Protection—Sparking Interest
By Bob Hult, Bishop & Associates Inc.
 

A confluence of both mechanical and electronic packaging issues looming on the horizon will likely create a whole new set of challenges for system designers. Signal speeds are going up, while chip feature geometry and logic voltage levels are going down. Smaller transistors, densely packed on a chip, typically increase the sensitivity of the device to high voltage surges. A high-voltage spike can corrupt a high-speed data stream, or worse yet, permanently damage the device.

Manufacturers of electronic products have always faced the destructive effects of sudden user-generated voltage surges, and have utilized a combination of defenses at the system, PCB, and chip levels to combat the problem. As chip transistor sizes shrink, susceptibility to damage increases. The profusion of portable devices exposes a greater range of electronic products to unwanted spikes in voltage.

The generation of an electrostatic charge is the culprit, and occurs as the result of a simple mechanical action. The amount of charge created between two surfaces depends on the properties of the two materials, degree of friction, speed of separation, as well as relative humidity. Typical static voltages generated with common activities include:

 Walk across carpet—10,000 volts
 Walk across tile—5,000 volts
 Working at bench—1,500 volts
 Removing ICs from protective tube—700 volts

Anyone who has drawn a quarter-inch arc between a wall switch and their finger has experienced the power of an electrostatic discharge. The result is a mild sting to the finger, but would prove deadly to an integrated circuit. Protecting a system from electrostatic discharge (ESD) is becoming a critical element in electronic product design. There is a differentiation, however, between component IC pin ESD events and the system level ESD. With safe handling and control methods, only a minimum ESD protection is required for the IC pins. Pins that interface with the outside world, however, must meet higher levels of ESD protection. These two issues require different protection design strategies.

A typical ESD event is characterized by an extremely rapid high-voltage, low-power spike.

Over time, Moore’s Law of expanded computing power and shrinking semiconductors has exacerbated the ESD protection problem. Integrated circuits of 20 years ago were relatively large and slow, making it easier for designers to add the necessary ESD protection circuitry on the periphery of an IC. New devices can be 1/20^th the size of their predecessors, leaving little space available for ESD protection.

The problem will become even more pronounced as IC manufacturers head toward devices based on 32 nanometer features.

This IC size reduction directly impacts the dielectric materials chosen to fabricate chips. These have specific limits of resistance to increasing voltages, and to a large degree affect the spacing between conductors. If these limits are exceeded, the dielectric can be punctured and voltage breakdown occurs. Circuit damage can take the form of circuit splatter/fusing and shorting, reduced breakdown voltage, increased leakage current, or complete circuit failure.

Another potential risk of an ESD event is electrical overstress (EOS). Applying a voltage that exceeds the device rating can result in latent damage that may not result in circuit failure until some future point in time. An ESD hit can weaken a device that may shorten its service life or make it more susceptible to subsequent voltage spikes in the future. This type of latent failure mechanism is extremely hard to detect or predict. Product burn-in and stress testing can often force the failure to occur and permit repair, but adds cost. Recognition of both ESD and EOS requires proper analysis and identification of their respective root causes to eliminate potential failures.

ESD can come from a variety of sources. In an effort to quantify their potential for damage, as well as the likelihood of ESD occurring in specific applications, a series of models have been developed. In 1980, the Human Body Model (HBM) was created as an ESD standard to simulate the handling of chips by people during assembly. HBM was followed by a Machine Model (robots), and Charged Device Model (chips moved by conveyors). In early 2000, the proliferation of handheld electronics and portables led to the introduction of a System Level ESD Standard to simulate ESD events occurring at the user level. System Level ESD events are much more damaging than Human Body Model ESD due to the increase in current from ~ one amp at 2000 volts HBM to 30 amps at 8,000 volts. Following this same trend is an emerging specification, Cable Discharge Event (CDE), which simulates the plugging of USB and Ethernet cables into electronic equipment. People who handle electronic products, both in the manufacturing process as well as the end user, are primary sources of damaging ESD. The human body model represents the average 100 Pf capacitance and 1500 ohm resistance of a human, and is commonly used to quantify the ESD sensitivity of electronic components.

Individual chips are designed with internal circuitry that allows the device to withstand the human body and machine model voltage levels. Integrated circuits are typically classified by their resistance to HBM ESD events. Class 1 devices are sensitive to voltages of 1,000 volts or less. Class 2 devices are sensitive to voltages between 1,000 volts and 4,000 volts. Class 3 devices are sensitive to voltage greater than 4,000 volts up to 15,000 volts. Rapid advancements in IC technology and the ever-increasing demand for circuit performance speed are not allowing the historically assumed safe HBM and MM levels to be met with protection design at the IC pins. A current controversy swirling within the supplier and user community is a proposal to reduce the human body model from 2000 volts to 1000 volts, and the 200-volt machine model to 30 volts. This effort is being driven by the realities of physics and the aversion to increasing chip sizes to accommodate legacy ESD protection standards. If accepted, the effect would shift greater responsibility for ESD protection to the OEM. Chip manufacturers claim that the old standards are “overkill,” and lowering the voltage limits would have no effect on device reliability. Strong opinions exist on both sides of this issue.

Protection of ICs from damaging ESD occurs at every step in the life of an electronic product. Personnel wearing special anti-static clothing and grounding straps manufacture chips in static-controlled areas using ionized air to dissipate static charges. The level of static charge on workers is confirmed to safe levels before entering the production area. Finished chips are packaged in anti-static tubes to insure protection during subsequent handling and shipment to the user. Automated chip handlers and robotic placement equipment maintain low impedance grounding to drain any static buildup during the PCB stuffing process.

Insuring that static discharges cannot damage a device in applications is the responsibility of the I/O design engineer. A properly grounded case is often sufficient to shunt an ESD pulse around sensitive circuitry, but I/O ports can provide a direct path to internal components.

The most effective location for protection is at the closest point to where the voltage pulse is entering the equipment.

An effective device should be capable of clamping an incoming voltage surge to a level within the operating range of sensitive components. Since ESD events are extremely fast pulses, a clamping transient voltage suppression device must be capable of responding quickly to voltage spikes of several thousand volts. They must also consume little valuable PCB and IC real estate, add minimal cost, and be applied using conventional automated placement equipment.

A variety of components including ceramic capacitors, zener diodes, metal oxide varistors or transorbs can be used to limit the voltage delivered to a circuit during an ESD event. Each has its own advantages and shortcomings. Ceramic capacitors are used to block high voltages but can degrade high-speed signals. Zener diodes can be used, but may be limited in high-speed performance and clamping voltages. Multilayer varistors work well in high-voltage applications, but their high capacitance can degrade high-speed signals, and may exhibit low DC breakdown. Many of these devices are available in surface mount packages, making them easy to install very close to I/O connectors. Few of these solutions can respond to sub-nanosecond ESD events.

A more effective solution is to block high-voltage spikes at the external interface itself, ensuring that voltage spikes never enter the equipment enclosure. The connector is typically grounded to the chassis of the equipment providing an ideal low-impedance ground path. Incorporating voltage suppression within the connector is also a more efficient use of space. Several connector manufacturers who specialize in EMI protected connectors also incorporate ESD clamping features.

Sabritec, for instance, offers military circular connectors that incorporate a diode matrix on each contact position to shunt voltage spikes to ground. Custom arrangements can also be created to provide protection from electromagnetic pulses created by a nuclear explosion.

Other common commercial I/O interfaces, such as Universal Serial Bus (USB), can include EMI filtering as well as ESD protection.

Littlefuse, a major supplier of discrete ESD components, offers their PulseGuard® polymetric connector array, which are designed for D-subminiatures connectors. Array strips are simply pressed over either the mating face or solder tails to add ESD suppression to the standard interface.

One of the most recent entries into the world of ESD protection utilizes innovative thin film technology, which promises lower trigger voltage levels, sub-nanosecond clamping response time, and low capacitance. EPI-FLO™, being developed by Electronic Polymers Inc., is a passive polymer formulation laminated between copper foils to create the EPI-CORE™ laminate, which can be formed into connector arrays using standard lithography and printed circuit board processes. It tolerates multiple high-voltage pulses of up to 25,000 volts without damage, is less than 5 mils thick, and features exceptionally low capacitance, in the order of less than 500 femto-Farads. This unique approach can be implemented directly in, or on, chip packages for ESD protection during manufacturing and packaging. They can also be provided as discrete components for surface mount onto a PCB, or integrated into a variety of connectors.

Advantages of EPI-FLO material include:

1. Consumes no PCB space as a connector array

2. Is lightweight

3. Does not interfere with GHz signals

4. Is bi-directional

5. Is readily customized to fit individual connector designs, including double and triple USBs.

6. Withstands lead-free soldering and typical environmental standards

The exceptionally low profile of EPI-FLO arrays allows easy adaptation to standard connectors. Users have the option of utilizing transient voltage suppression in the initial design of a new product, or adding it after production reveals an ESD problem. One of the first applications has been in USB connectors, which have become an industry standard I/O in a huge variety of consumer and commercial products. Work is also being done to develop a RJ-45 Ethernet ESD-protected interface. Electronic Polymers offers ESD test services to demonstrate the effectiveness of the EPI-FLO solution.

Many applications are expected in the cell phone, laptop, PDA, notebook, personal entertainment, computer peripheral, and network hardware markets.

Bishop & Associates Comments:

• As semiconductor device geometry continues to decrease, concerns about the damaging effects of electrostatic discharge are increasing.

• As more products decrease in size and become portable, the likelihood of exposure to ESD increases.

• A system level ESD strategy includes both PCB design, as well as I/O circuit protection elements.

• Recent proposals to lower the ESD standard for semiconductor devices will likely allow the design of high performance ICs with safe handling, while the System Level ESD will continue to become an important focus for pins with external interface.

• Changes in chip ESD standards will drive the development of more effective strategies for transient voltage suppression at equipment manufacturers.

• Metal enclosures can protect internal circuits from ESD, but the I/O port can provide a direct path to sensitive electronic devices.

• A variety of PCB-mounted components, including diodes, capacitors and varistors, can effectively limit high-voltage surges but consume valuable PCB space, and may distort high-speed signals.

• Effective voltage clamping within the I/O connector may be the most effective and efficient solution to ESD protection.

• Emerging technologies, such as EPI-FLO, offer greater transient voltage suppression capabilities with low trigger and clamping voltages, sub-nanosecond response times, the ability to support multiple high-voltage spikes, and exceptionally low capacitance.

• The EOS/ESD Association (www.esda.org), based in Rome, NY, is an industry association dedicated to promoting the exchange of technical information in the field of electrical overstress and ESD.

Robert Hult
Director of Product Technology, Bishop & Associates, Inc.
Robert Hult has been in the connector industry for over 36 years. Hult began his career as a sales engineer for Amphenol. He joined AMP in 1972 and served in several management positions through 1996. In 1997, Hult joined Foxconn as group marketing manager for Intel, Chandler, Arizona, U.S.A. Prior to joining Bishop & Associates, Hult was the regional application engineering manager for Tyco Electronics.

Hult graduated in 1968 from Bradley University with a Bachelor of Science degree in electronics technology and a minor in business.