Changing Landscape of Test and Burn-In Sockets

By John MacWilliams, Bishop & Associates Inc. and
Dr. Tom Di Stefano, Centipede Systems Inc.

It is often said, “The more things change, the more they stay the same.”

This can perhaps be said about test and burn-in sockets, in that there are a cast of players who have evolved with the industry, but the distinct test and burn-in market seems to have remained pretty much intact. Evolutionary improvements in test and socket technologies have occurred—in density and performance—but testing methods have been slow to change, even in the semiconductor industry. Test methodologies have been proven over years of experience in large numbers of embedded capital equipment, and it will take a lot to create change.

It may be that now, however, forces are converging to make major changes happen. These include: 

• Performance requirements on the very edge of socket design capability

• IC test costs are becoming intolerable and will dictate radical change

• Burn-in costs/unit in semi-commodity memory products require merging/changing test methods

• Shift in IC packaging designs toward SiP, CSP, and flip-chip configurations

• Wafer scale packaging and test regimes may differ from discrete socketing

• Testing multiple devices at once, i.e. test-in-tray technology, is in the offing

Test and burn-in sockets represent a relatively small, but technically challenging, segment of the more than $40 billion connector industry. Thus, test socket manufacturers tend to be a separate breed from production connector manufacturers. Their business postures involve high levels of engineering, low-volume/high-tech/high-ASP manufacturing, and typically a different set of customers than high volume production connector companies. 

• Designs are very robust, with hundreds of thousands of touchdowns, often requiring replaceable contacts.

• Socket costs that are in the tens to hundreds of dollars—not pennies, like many production sockets.

• Test socket manufacturers are typically a different breed from production connector makers.

• The market for test sockets is closely associated with IC manufacturing, not electronic equipment.

• Other test applications, such as breadboarding and adapters, fall generally into this category.

Since many test and burn-in sockets are closely linked to silicon packaging and technology trends, including some of the most demanding requirements in the connector industry, they may have some or all of the following characteristics: 

• Highest speed and edge rates

• Highest density, approaching IC pad densities in the 6-10 mil range

• Lowest voltages and noise margins

• Rigors of high-temperature, burn-in test

• Impact of Moore’s Law on successive generations of chips and discrete interconnect devices

• Backdraft from increasing IC test costs

• Threats from wafer level/flip chip, MEMS (Micro-Electro-Mechanical Systems), 3D, and other wafer/die-level test technologies

• Semiconductor performance—electrical, mechanical and density—continues to increase, approaching limits of conventional socket technology. Recent slowing of Moore’s Law indicates showstoppers may be further in the future than originally thought.

• Semiconductor test costs are a critical issue for the semiconductor industry. This places financial pressure on the test supply chain, and will result in new test and burn-in strategies, such as combining test and burn-in, wafer-scale test, and test-in-tray.

• IC packaging is changing, albeit slowly, toward flip chip and 3D chip packaging. Conventional sockets typically do not test unpackaged ICs (pad density below socket capability). This requires probe testing, including micro-pogo pin testing of pad pitches below discrete socket capabilities.

• Test socket makers continually face these new challenges, which are overcome each year with few, if any, roadblocks.

Test Socket Technology Trends

Key technologies:

• Contact design for socketing of IC packages exceeding 10,000 touchdowns

• Contact design for fine pitch applications < 300 microns

• Contact design for BGA and LGA applications

• Engineered housing materials and design for rigorous test environments

• Electrical modeling and simulation at very high multi-GHz performance levels

Test sockets are used for package and die verification, device characterization, failure analysis, and debug. Once the package/device is characterized, the OEM generates a final test program, which is used with the test socket/contactors during large volume final test.

A key component of tests sockets is long insertion life without contact or pad degradation. Not all devices require such high performance. In some cases, production or burn-in sockets can be used as test sockets because the devices are inexpensive. In general, a long-life high-performance test socket will cost 10 or more times the cost of a burn-in socket, and deliver 300K to 500K insertions before a rebuild.
 
Key design issues for high-performance test connectors include: Ever lower voltages and faster edge rates. At lower voltages, connectors are getting noisier, by comparison, with higher crosstalk. With microprocessors dropping below two volts, required performance is now at what was considered threshold noise levels only a few years ago. With five volt TTL logic, and 20-80% as the unknown state, there used to be a low-end level of ~1 volts. Today, one volt is very close to the high. 
 
Thus, what was the noise ceiling a few years ago is now the Logic 1 floor. Edge rates are getting faster, with tighter timing window requirements. Even if a part only runs at 250 MHz, edge rates are important, because that part may be syncing with another running at 3GHz. Thus, when the part is clocked it has to change state as though it were a 3GHz part. If it didn't, it would miss the time window, or cause a latent state, as it took two to three clock cycles to change state. This requires connectors that do not delay or distort the signal—especially in test. Crosstalk is one of the bigger issues. It appears the answer is LVDS, (Low Voltage Differential Signaling).
 
There is also the need for lower force connectors that do not crack thinner die. This is especially true of large devices, which include BGA, LGA, etc. The die is made thinner to increase performance, reduce cost, etc., but the pin count is rising, up to 10,000 I/O on the roadmap for some server ASICs and CPUs.
 
Consider how many discrete devices it used to take to assemble a PC board. Over time, these functions were integrated into a single die. Now, IC manufacturers are beginning to use different fabrication techniques on the same die (e.g. multi-core, logic, and memory). As functions are integrated, there is an increased demand for higher frequency sockets to test larger BGA packages. In addition, bus structures are now high-speed serial vs. parallel, all leading to higher speed socket requirements. 

Multiple Package Test
This significantly changes single package test and burn-in socket design. Multiple package testing (see test-in-tray below) has been happening for quite some time. Tester resources and cost have limited this trend. Requirements for higher speed on more pins simultaneously is a limitation. Improvements are steady year to year; the cost of testers is the bigger issue. There are no real roadblocks, just a consistent progression. A big issue in memory is 128 moving to 256 devices in one insertion, tri-quad, and possibly octal, has moved to higher-end analog and RF testing, and has already moved to strip testing on low-cost parts.
 
Wafer Scale Test
Wafer scale test reduces or eliminates the need for package testing. The requirement for a membrane type vertical socket that can handle high frequency, high density, and high touch-down counts is still in the future. There are developments in process that will be more evolutionary than revolutionary. Keeping the cost per pin to a reasonable level for probe cards, probe stations, etc., and being able to replace pins at a reasonable cost, is where the industry needs to be. This requires significant R&D costs, with unsure returns.  
 
Pad Pitches for Wafer Scale
Pitches in the four to six mil range, such as in bare-die testing (i.e. wafer probes), will require new technology. These include micro-spring/MEMS-type contacts and PTFE/elastomeric interposers, all new technologies to connectors. Micro pogo-pin designs hold some promise. (See Aries Electronics’ developments online.)
 
Burn-In
Reduction/elimination of burn-in, or combining test with burn-in due to cost pressures (began c. 2000), is already fact in some memory devices (Flash) and is expected to increase in use.
 
Test-in-Tray Technology
There is a growing consensus that test and burn-in (TBI) requires a new approach. SEMI’s CAST consortium is the latest effort to focus on an aspect of this looming problem. TBI consumes an increasing portion of the manufacturing cost of semiconductor devices (up to 20% in some cases). The problem continues to worsen as test time grows with increasing device complexity.

Test-in-Tray technology has the potential to greatly reduce the cost of TBI, initially by enabling parallel test of trays of devices with rapid index times. Only ATE (automatic test equipment) resources limit parallel test. Test-in-tray has the potential to reduce the aforementioned escalating test costs, particularly with new wafer scale packaging, CSP, and flip chip devices. Adoption is slowed by sunk costs in legacy equipment and by risk-adverse contract test houses. The test-in-tray approach provides the test efficiency of strip test without limitations on device types. Trays can handle all package and device types, from large BGA/LGA packages to WLP and bare die formats, all with the same automation transport standards.
 
Initial adoption of test-in-tray methods is in MEMS and automotive electronics, which require extensive testing. As alignment accuracies improve, WLP and other fine pitch devices will be tested in trays that allow automated burn-in and test sequences in a more cost-effective format than with probe cards on wafers.
 
Contactor technology is increasingly important and critical to the operation, testing, and burn-in of semiconductor devices.
 
Testing trays of mostly good devices allows more effective use of ATE resources than testing unyielded wafers. Bare dice are transported with a minimum of human intervention.
 
With full test-in-tray automation, devices remain in a tray throughout back-end processing, including all test and burn-in steps, speed sort, trim, post-processing, marking, and packing. Standardized tray carriers enable automatic handling throughout, with a minimum of intervention. “Lights-out” test automation reduces handling and custom fixturing to allow cost-effective production anywhere in the world. Standardization allows reconfigurable modules of automation to handle any device type with a minimum of change time. Tray carriers promise manufacturing efficiencies for the back end that standardized FOUP transport has enabled for wafer fabrication.
 
Test-in-tray automation extends the capability for forward and backward data traceability for rapid learning. Integrated data from TBI operations enables rapid learning and a steep learning curve for competitive advantage. With lights-out production, the test floor can be configured to increase rapid learning rather than to simply save labor costs.

Table 1: Test-in-Tray Automation Roadmap
Source: Centipede Systems Inc.

Centipede Systems supports the rapid adoption of test-in-tray into a wide range of applications, from complex MEMS to high-density TSV (through-silicon via) devices. Information is provided to semiconductor manufacturers, and to the essential infrastructure for automation equipment, ATE, burn-in, contactors, and sockets. A section on standards is dedicated to proposed outlines for transport carriers, trays, and contactors. Adoption of a basic set of standards is essential to the rapid growth of this emerging test-in-tray industry. A growing array of resources is provided here to facilitate adoption of standards, protocols, and equipment needed for test-in-tray.
 
Further reading: Access Dr. Di Stefano’s article, Lights Out!, online.
 
Dr. Thomas Di Stefano is the co-founder of Tessera Inc.; a chip-scale package inventor; founder and president of Centipede Systems; and a micro-interconnect, TnT test, and burn-in inventor. Learn more about Centipede.

Centipede’s Test-in-Tray technology greatly reduces the cost of burn-in and test, which has become dominant in manufacturing of high value semiconductor devices. “Lights-out” automation reduces handling and custom fixturing to allow cost-effective production anywhere in the world.

John MacWilliams Senior Consultant and Analyst, Bishop & Associates Inc. John MacWilliams, a senior consultant to Bishop & Associates, has 40 years of diverse experience in the electronics industry. He has worked in sales, market development, and management positions for IRC, TRW, AMP (prior to TE), and his consultancy, US Competitors LLC. He authors the connector chapter for the International Electronics Manufacturing Initiative, and has a website, Electronics Industry. John is a graduate of Lehigh University and resides near Newark, DE.