DDR4 is Coming (But so are 3D/TSV and Surface-Mount)

By John MacWilliams | July 15, 2013

DDR4 is Coming (But so are 3D/TSV and Surface-Mount)

Computer memory has experienced many evolutions and revolutions since its beginnings in the early PCs of the 1980s. Modern Dynamic Random Access Memory (DRAM), while more or less a semi-commodity, is one of the highest-tech chip designs in the semiconductor industry. It has gone through several refresh cycles in the past decade, from the original double data rate synchronous dynamic random-access memory (DDR/SDRAM) through double data rate type 3 (DDR3) and a somewhat aborted digression into Rambus DRAM or RDRAM. JEDEC, the Joint Electron Device Engineering Council, founded in 1958 by EIA, has been at the forefront of DRAM standards creation, including standards for DIMM (dual in-line memory module) packaging.

Several converging forces are at the center of DRAM developments:

Moore’s Law has improved industry-leading DRAM scaling from microns to about 20nm feature sizes.
DRAM will approach the “molecular wall” facing semiconductor technology somewhere around 2020.
Industry leaders are working on emerging research devices (ERD) and materials (ERM) beyond the 10nm node.
Current DRAM chip designs have enabled Gigabit speeds and wider bandwidths with low bit error rates.
Some say future HPC requirements will be 10-fold what they are today; i.e., a quantum leap may be required.
Chip packaging advances include SMT, flip chip, 3D stacking, and surprisingly resilient DRAM PCB and socket designs.
High-volume, low-cost PCs and set-top boxes vs. high-performance server and workstation specs
Boom in super-high-volume mobile/handheld applications, from SODIMM to mostly direct-attached memory
Advent of non-volatile technology (flash) has greatly expanded the application of memory devices.
Emerging technology in 3D/TSV, even stacked with the CPU, will provide the next leap in performance: the ultimate brick logic/memory stack, circa 2018-20.

JEDEC finalized the DDR4 specification in September 2012. It is expected to hit server applications first, where its initial higher price can be justified, and then reach PCs later, as the prices drop. The advantages DDR4 offers could help the PC market get out of its current doldrums, but it’s more urgently needed in servers for two main reasons — it will help reduce power consumption and keep pace with advances in CPU speeds. In current server designs, memory banks are a significant drain on power, having increased to 40% or more of the total power budget. Thus, the 1.05-1.2v spec on DDR4 versus 1.2-1.65v for DDR3 will be somewhat important. Chip speeds will increase from a low of 800Mb/s for DDR3 to 1.6Gb/s for DDR4, which will top out at 3.2Gb/s over time.

There will be multiple packaging versions of DDR4, including a 284-pin vertical DIMM socketed on 0.85mm pitch and a 256-pin small outline DIMM socketed on 0.5mm pitch. There will be other variants to this packaging, including an ultra-low-profile flush-mount single-sided socketed SODIMM (small outline dual in-line memory module) being promoted by Micron and TE Connectivity. Beyond DIMM socketing, surface-mount DDR4 will come into play in some applications, such as ultrabook PCs, set-top boxes, and embedded systems.

Mechanical package outlines for DDR4 can be found here, covering the 284- and 256-pin designs. These sockets are an extension of DDR3 240- and 204-pin, 1.0 and 0.8mm pitch DIMM designs. DDR4 may signal the last iteration of socketed DRAM packaging. They will last, with several improvements in performance, until approximately 2020. Initial DDR4 server production will occur in 3Q13 in high-end units, accelerating into 2014-15. PC applications will also appear late this year, rushed into service to bolster sagging PC sales, but full production may not occur until 2015-16, unless prices come down faster. It is rumored that Intel’s Haswell-E processors will be compatible with LGA2011 and LGA2013 as well as DDR4 DIMMs. It is likely that Haswell-E will migrate to Broadwell and Lituya Bay CPUs in late 2014 — all with DDR4 support.

By 2020 — and for many mobile products, now — DRAM will be surface-mounted. Playing to that form factor will be both higher chip capacities and limited headroom in mobile products. The “brick” we spoke of above will of necessity be some form of SMT. One question will be how, and if, these 2020 millennial DRAM products will have upgradeable memory. Another issue, which is bubbling up right now, is a potential paradigm shift in HPC to a new form of ultra-low-power microchips, a monolithic CPU/memory breakthrough, or other direct-chip communication design strategies. Beyond that, research labs are working on new forms of memory, such as magneto-resistive memory (MRAM) and scalable Phase Change Memory (PCM), which may be first used in non-volatile (flash) applications. Long-term, connector companies need to follow developments in the semiconductor industry.

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John MacWilliams

Market Segment Director-Computer, Peripheral and Consumer at Bishop & Associates Inc.

John has enjoyed a long and diverse career in the electronics industry, including management positions with IRC, TRW, AMP, and his own company, US Competitors LLC. He is the author of many industry articles, including past and current iNEMI.org connector industry roadmaps, US government competitiveness initiatives, and numerous Bishop Reports on the computer and consumer electronics industries. He is an outspoken supporter of the future of US manufacturing in a global marketplace. John is a graduate Lehigh University in Bethlehem, Penn.

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