Replacing traditional signaling with four-level pulse amplitude modulation (PAM4) may be exactly the solution the industry is looking for.
System design engineers have been dealing with the challenges elicited by ever-increasing data rates for many years. High-speed connector manufacturers have collaborated with their bleeding-edge customers and chip manufacturers to develop cost-effective interconnects that deliver a high degree of signal integrity. A combination of low-voltage differential signaling, improved PCB laminate materials, optimized connectors, and advanced signaling conditioning, along with enhanced PCB fabrication techniques, have allowed system speeds to evolve from hundreds of megahertz to 25+GHz, and even higher speeds have appeared in designer’s roadmaps for next-generation products.
Today, backplane connectors have been demonstrated to 28Gb/s non-return to zero (NRZ), while I/O connectors typically aggregate multiple lower-speed channels to achieve higher throughput. The current crop of flagship backplane connectors has been optimized in terms of attenuation, crosstalk, skew, and signal density, but may only have one more iteration of such performance improvements in them. Fiber optic interconnects have been waiting in the wings for years, but concerns about cost and power consumption have prevented broad adoption thus far. Still, the same question keeps popping up: What will be the practical limit of copper interconnects?
An ideal short-term solution would be the ability to double the data throughput using legacy connectors and backplanes. This approach would allow engineers to utilize their experience with existing connectors and avoid suffering through a learning curve with a new connector family. System designers and project managers generally prefer staying in their comfort zone to avoid risk. With this solution, electronic equipment manufacturers could continue to use documented processes, installed equipment could be upgraded in place by repopulating existing backplanes with next-generation daughtercards, and connector manufacturers could avoid a costly upgrade of existing connectors with marginal improvements. So, replacing traditional (NRZ) signaling with four-level pulse amplitude modulation (PAM4) modulation may be exactly what the industry is looking for.
Unlike NRZ encoding, which provides only two levels per machine cycle, PAM4 features four levels, essentially doubling the number of bits transmitted without increasing the bandwidth of the channel. The result is that a channel operating at 12.5Gb/s can deliver 25Gb of data and a 25Gb/s channel can deliver 50Gbs of data, which is the best gift the industry could hope for given the combined pressure of increasing data rates, adversity to risk, and ever-present demands for reduced cost.
As with most gifts, however, there are some serious strings attached. The advantage of doubled data throughput introduces additional design issues that must be addressed to ensure reliable performance. Since each cycle is now broken into four levels at the same amplitude, the signal-to-noise ratio is much reduced, making it harder to detect each level. Additionally, the PAM4 vertical eye opening is only one third of NRZ, making it more susceptible to noise. Clock recovery is also more difficult, and the use of PAM4 modulation may result in more inter-pair skew, jitter, and channel loss. Further, inter-symbol interference (ISI) may behave differently in a PAM4 channel. Even tiny channel impedance mismatches can result in reflections that are more detrimental than insertion loss or crosstalk. Currently, though, there are few established standards to check such designs against, so new design test and verification tools are required. The successful utilization of PAM4 signaling will also likely require the use of advanced equalization technology, as the bit error rate (BER) of these systems is sure to suffer the impact if these issues are not addressed. Lastly, power consumption related to the compensation of these negative factors in PAM4 applications may increase as well.
However, in spite of these challenging issues, PAM4 appears to be the preferred way to achieve 56+Gb data transfers.
New 56G PAM4 serializer-deserializers (SerDes) are entering the market. Avago Technologies has demonstrated a 56Gbps PAM4 SerDes for copper backplanes and optical interconnects targeting next-generation switches and routers. Credo Semiconductor demonstrated its single-lane 112G PAM4 short reach (SR) IP solution and long reach (LR) 56Gb/s PAM4 at a recent technology symposium. Intel sees PAM4 signaling as a key technology to enable next generation computers to efficiently support the transfer of zettabytes of expected annual data traffic.
Standards organizations are also getting on the bandwagon, including OIF and Ethernet. The 400GbE task force (802.3bs) adopted PAM4 based on 8 x 53.125Gb/s signaling.
Live channel demonstrations using PAM4 technology were ubiquitous at DesignCon 2017. Leading backplane connector manufacturers showed backplanes running both NRZ to 25Gb/s and PAM4 signaling at 56Gb/s. It has become necessary to determine NRZ or PAM4 signaling when comparing connector performance ratings.
The adoption of PAM4 signaling technology opens the door to higher speeds without a forklift in basic interconnect technology. However, it introduces its own challenges to successful circuit design. The next step will be to solve them.
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