Higher speeds have pushed designers to find creative ways to manage conflicting issues of speed, density, signal integrity, and reach. But as we look past 112Gb/s, the picture is getting fuzzier.
Traditional backplane architecture has served the electronics industry exceptionally well for nearly 70 years. The advantages of modularity, manufacturability, repairability, as well as the option to upgrade performance made it the design of choice. Standards organizations created a series of specifications that insured performance as well as intermateability between competitive suppliers. Backplane laminate materials have experienced a continuous evolution, from phenolic paper to today’s advanced fiberglass and epoxy that reduces high-frequency loss. Circuitry on the backplane progressed from point-to-point to bus structured and meshes. Backplane connectors evolved from one-piece edge-card to highly refined two-piece connectors capable of supporting multi-gigabit data rates.
As speeds increase, signal loss and distortion reduces the practical length of the channel. In order to address the challenge of higher speed systems, backplane connector designers developed variations of the traditional copper backplane, such as the midplane, where daughtercards are plugged into both sides of a centrally located backplane.
In order to further shorten the signal path between daughtercards, engineers introduced the orthogonal midplane, where the daughtercards on one side of the midplane are oriented 90° to those on the backside.
Orthogonal direct connectors eliminated the loss and distortion introduced by the midplane, enabling daughtercards to mate directly.
Although most production systems today operate in the 12 to 25Gb/s NRZ range, the industry demands a clear migration path to 56Gb/s in order to support higher data rates anticipated by next-generation equipment. 112Gb/s PAM4 channels have already been demonstrated and are in the process of being standardized by the IEEE and OIF. Designers of high-performance computers will be the first to require 56Gb/s+ performance, but demand will eventually trickle down to more commercial equipment. Designers must balance often conflicting issues of speed, density, signal integrity, and reach.
Keith Eichmann, director of business development and product management at Amphenol ICC, commented that systems that operate at these extreme speeds typically involve some degree of interface customization in order to satisfy the specific mechanical and electrical requirements of the application. A close working relationship with the selected connector vendor has become part of the normal design and qualification process. The challenge has become the ability of interconnect systems of all types to keep up with the amazing advances in silicon technology.
Existing flagship high-speed backplane families such as the Amphenol ICC Paladin, Molex Impulse, and TE Connectivity’s STRADA Whisper connectors continue to be optimized with incremental upgrades rather than be superseded by a newer generation. Refinement for signal integrity requires that every millimeter of the channel is modeled and analyzed including optimized PCB launch designs and layout rules. Entirely new backplane connector families may be introduced in the future, depending on the development of new materials, design, or silicon technologies or changes in the direction of the market.
In order to address bleeding-edge applications today, leading connector suppliers, including Amphenol ICC, Molex, Samtec, and TE Connectivity, are recommending the use of orthogonal direct architecture or cable backplane architecture that replace the traditional backplane panel with a series of shielded differential pair cables. “Flyover” cables (i.e., shielded cable routed over PCBs) are also in consideration to reduce channel loss. Loss and distortion can be better controlled in shielded cables, but cable management and system cost are factors that could limit cable backplanes for mass market applications.
Highly optimized state-of-the-art backplane interfaces have demonstrated the ability to support 56Gb/s NRZ signaling and up to 112Gb/s using PAM4 signaling. Amphenol ICC has been shipping Paladin cable backplane assemblies for several years. TE Connectivity recently expanded its STRADA Whisper cable backplane system with a 4- row, 8-column 100 ohm header that is terminated with Madison TurboTwin differential pair cable.
Taking the highest speed signals out of the board entirely via shielded differential cable is becoming an increasingly attractive option.
Samtec has been promoting its FireFly flyover concept that transitions high-speed signals to copper or fiber optic cables that “fly” over the daughtercard to a backplane or I/O port.
Samtec’s AcceleRate families of direct attach cable assemblies offer exceptional signal density with the ability to support 112Gb/s PAM4. New NovaRay high density stacking and cable connectors deliver 112Gb/s PAM4 channels. Samtec and Molex recently announced a licensed source agreement to develop solutions to address 56 and 112Gb/s data speeds.
Molex announced its BiPass I/O connector, which provides a flyover link to a ZQSFP pluggable interface.
TE Connectivity beefed up its low-profile internal connector line with the Sliver PCB connector, which is ideal for short internal flyover applications.
Mid-board optical transceivers such as the Leap® On-Board Transceiver from Amphenol ICC can be mounted immediately adjacent to a processor or ASIC to minimize signal degradation introduced by the PCB. A new specification recently released by the Consortium for On-Board Optics (COBO) should help bring order to the optical transceiver market.
In an effort to eliminate even the short PCB traces between a processor and an adjacent connector or optical transceiver, Intel introduced the Xeon Phi processor, which utilizes an LGA socket with an integrated copper connector and cable assembly that links directly to two QSFP28 I/O receptacles.
The question is where do we go from here? Once we get past 112Gb/s, the crystal ball becomes fuzzy. We may be years away from silicon that operates at anticipated 200Gb/s+, but continuing demand for increased bandwidth keeps system engineers up at night.
A survey of high-speed connector product managers and signal integrity gurus turned up little consensus, with some simply acknowledging that it remains an open issue. Several indicated that 112Gb/s NRZ may be possible but not likely, nor is the adoption of PAM8 signaling, which would reduce margins and increase loss as well as require the development of a new generation of SERDES devices. Scott McMorrow of Teraspeed Consulting and CTO SI Group at Samtec predicted that achieving short reach 224Gb/s PAM4 copper channels may be possible, depending on advanced chip technology. Perhaps a combination of multiple technologies, such as daughtercard flyover and cable backplane, may extend the life of copper interconnects architecture.
Optics have been under consideration for many years, but advanced PCB materials and active signal conditioning, along with improved connector design, kept traditional copper interfaces the most cost-effective solution. Leading connector manufacturers continue to invest in research of optical solutions, including embedded optics, but current products generate little production interest. Advanced research into true silicon photonic devices continues, but raises additional issues. Integration of a photonic engine with a high-speed processor would result in some serious power consumption and thermal dissipation issues. Increasing cooling airflow creates a greater opportunity for dust contamination at the optic interface.
In spite of these challenges, the confluence of the laws of physics, cost of advanced copper and silicon components, demand for increased signal density, and falling prices for optical components may finally begin to tip the scales to favor optic solutions. In the short term, optics will likely remain a last-ditch solution until copper alternatives are unable to support required data rates. We may finally be nearing that point.
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